The application relates to semiconductor devices and to methods for fabricating semiconductor devices, and more particularly to a method and structure for fabricating a tiled-stress-alleviating pad structure for use, for instance, in back-end-of line (BEOL) and/or far back end of line (FBEOL) semiconductor structures.
As the density of circuits, such as multi-core or application-specific integrated circuits (ASICs), continues to increase, many designers are working towards three-dimensional (3-D) stacked chip technology as an emerging trend in the industry. By way of example, during conventional far back end of the line (FBEOL) processing of 3-D stacked chip fabrication, metal pad layers are traditionally employed to support a controlled collapse chip connection (C4) element and the corresponding ball limiting metallurgy (BLM) layers. Disadvantageously, these pad layers which, for instance, may include, or be fabricated of, aluminum or aluminum alloy, may have a higher coefficient of thermal expansion (CTE) compared to other components of the 3-D stacked die. This CTE mismatch may result in significant thermal-mechanical stresses being generated in the metal pad layer and other layers of the 3D-stacked die during the subsequent processing steps, resulting in undesirable delamination and/or cracking of the pad layer which, in turn, may impact yield, and thereby increase costs.